Technical Field
The technology relates to methods for analyzing timing delays in digital integrated circuits.
Discussion of the Related Art
Design and evaluation of high-performance, digital integrated circuits typically involves numerical simulation of transistor performance and logic element switching speeds, or edge-rates, in complex circuits. Often, simpler circuits such as a ring oscillator 100 depicted in FIG. 1A are simulated and/or fabricated to gain a basic understanding of a transistor's, or logic element's, edge-rate performance. Knowledge gained from a circuit element's performance in a ring oscillator can be used in models that incorporate the circuit element in more complex digital circuits, such as microprocessors.
A simple ring oscillator may include an odd number of inverters 105 connected in a loop as depicted in the drawing. For such an oscillator having m identical inverters, where m is an odd positive integer, the oscillation frequency f is related to the timing delay dT introduced by each inverter according to the following relation.
  f  =      1          2      ⁢      mdT      
In general, timing delay introduced by a digital circuit element can depend upon gate or diffusion capacitances within the element, and also on loading of the element. A circuit element may be loaded in several ways. One type of loading is “fan-out,” where a single element may drive a plurality of circuit elements at its output. Another type of loading may be simple resistive loading due to long interconnects, for example. Conventionally, effects of loading can also be tested and simulated using ring oscillators in which circuit elements are loaded at each delay stage, as depicted in FIG. 1B. A loaded ring oscillator 102 may include m delay stages 111-119, and each delay stage may comprise a circuit element having its output loaded by more than one element.
For example, a delay-stage circuit 120 may comprise a first circuit element (inverter 103) in the loop path that is arranged in a fan-out configuration to drive N circuit elements (e.g., inverters 105). The multiplying symbol 122 represents the number of following circuit elements (inverter 105) that are driven in parallel by the previous circuit element (inverter 103). N may be any positive integer value that may be representative of a configuration used for the circuit element in a digital circuit that is being designed. For example, if an inverter is configured to drive 10 logic elements in a circuit under design, then N may be 10. In some cases, N may be 2, 5, 10, 15, 20, . . . 60 or higher values.
For the loaded oscillator 102 depicted in FIG. 1B, every circuit element along the loop path (e.g., inverters 103, 105) will drive an equivalent number N of circuit elements at their outputs. Accordingly, there is an “edge-rate balance” across each circuit element along the loop path. That is, there is a large edge-rate at the input and at the output of each circuit element along the loop path.
The loading of a circuit element adds a “timing penalty” or “timing error” to the circuit element. For example, the circuit element's nominal timing delay dT may be increased by an amount δ due to the loading: dT→dT+δ. The value of δ may depend upon the amount of loading. Conventionally, timing errors for loaded circuit elements are determined using a loaded ring oscillator 102, as depicted in FIG. 1B. The timing delays may be calculated from numerical simulations, and verified by fabrication of the oscillator and subsequent measurement of the circuit's performance.